3+ day, 2+ hour ago   (454+ words) 12-inch high-NA EUV masks; Arm’s edge AI push; Amkor’s expansion; 3D memory; FeRAM startup makes waves; Qualcomm-AWS $60B custom silicon deal; Ayar Labs’ scale-up deal; new iPhone chip and format; rogue OpenAI agents in Germany; fab factory; fine-pitch RDL tech for advanced…...

4+ day, 10+ hour ago   (591+ words) Discrete steps are being merged with others as dimensions shrink into the angstrom range. The lines between discrete semiconductor manufacturing processes are starting to blur at sub-2nm nodes as transistors continue to shrink, sensitivity to various processes rises, and the…...

4+ day, 10+ hour ago   (202+ words) How early RTL testability analysis and DFT optimization enable shift left strategies that improve manufacturing test quality, reduce turnaround time, and deliver early quality estimates. The post Accelerating Shift Left With Early RTL DFT Analysis And Connectivity Verification appeared first…...

4+ day, 10+ hour ago   (473+ words) By Guy Cortez, Dan Alexandrescu, and Aaron Barker The semiconductor industry has invested heavily in embedded monitors to gain visibility into advanced silicon. Those monitors are essential, but the next step is not simply to collect a larger volume of…...

6+ day, 10+ hour ago   (296+ words) Researchers from the National University of Singapore developed an atom-thin film of amorphous carbon designed to insulate increasingly thin copper interconnect wires. The film maintained a dielectric constant of 1.35 across thicknesses from 0.8nm to 2.7nm, withstanding strong electric fields while preventing copper…...

1+ week, 5+ day ago   (178+ words) Multi-die design is becoming indispensable for automotive applications, such as ADAS and IVI, addressing demands for reliability and safety. The post Multi-Die Design for Automotive Applications appeared first on Semiconductor Engineering. Electronics for automobiles sit in the middle of two…...

1+ week, 6+ day ago   (256+ words) Researchers from Ecole Polytechnique Fédérale de Lausanne (EPFL) debuted a new class of gallium nitride (GaN) transistor, called an intrinsic polarization superjunction (iPSJ), that can handle very high voltage with minimal energy loss. Made from layers of GaN on a…...

1+ week, 6+ day ago   (98+ words) Semiconductor Engineering Chip Industry Technical Paper Roundup: Sep. 1 Wafer-scale optical interconnects for LLM training; Rowhammer-based inference attacks; 3D-IC test cases; liquid cooling for 2.5D/3D packages; wafer-scale 2D semi growth; DL-based parameter extraction for 2D transistors; and chip-placement optimization. New technical papers recently added…...

1+ week, 6+ day ago   (815+ words) Part I – Pioneering work in developing CFET-critical modules: an improved backside contact module and a novel gate stack for threshold voltage tuning. By Cassie Sheng, Hiroaki Arimura, and Naoto Horiguchi The semiconductor industry is going through a major architectural transition,…...

2+ week, 3+ day ago   (173+ words) Researchers from Georgia Institute of Technology published a technical paper titled “Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation.” Abstract Excerpt: The paper analyzes “wafer-scale optical interconnects” for mixture-of-experts LLM training…...